1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a duty cycle correction circuit and operation method thereof.
2. Description of the Related Art
In general, semiconductor devices, such as double data rate synchronous DRAM (DDR SDRAM), perform a desired operation in response to different kinds of signals received from an external controller. Such semiconductor devices are developing toward a high-speed operation according to users' demands. For the high-speed operation of the semiconductor devices, a clock signal having a high frequency should be provided from the outside. The external clock signal is the source of an internal clock signal that is internally used in a semiconductor device, and the frequencies of the external clock signal and/or the internal clock signal determine the operating frequencies of the semiconductor device. Basically, if the frequency of the clock signal is high, the operating speed of the semiconductor device may be increased. An increase in the frequency of the clock signal, however, is limited. A variety of methods have been proposed to overcome the limit. One of the methods is a double data rate (DDR) method for enhancing the utilization of the clock signal.
The existing single data rate (SDR) method is, for example, a method of inputting/outputting data in response to the rising edge of a clock signal, whereas the DDR method is a method of inputting/outputting data in response to both of the rising edge and the falling edge of a clock signal. That is, two data is input/output in one cycle of the clock signal. Accordingly, more data may be processed in the DDR method than in the SDR method for the same period.
Meanwhile, to process data in response to both of the rising edge and the falling edge of a clock signal as in the DDR method, it may be important to maintain the duty ratio of a clock signal at 50:50. That is, the logic ‘High’ section of a clock signal must be identical with the logic ‘Low’ section of the clock signal. When the 50:50 duty ratio of a clock signal is broken due to a jitter component and other reasons, reliability of data input/output in response to the clock signal may not be guaranteed.
Furthermore, an increase in the frequency of a clock signal may cause difficulties in controlling the duty ratio of the clock signal. Accordingly, schemes for precisely and quickly controlling the duty ratio of a clock signal having a high frequency are in demand.